An FPGA implementation of 2-D CNN Gabor-type filter

SAATÇI E., CESUR E., Tavsanoglu V., Kale I.

18th European Conference on Circuit Theory Design, Sevilla, Spain, 26 - 30 August 2007, pp.280-281 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/ecctd.2007.4529591
  • City: Sevilla
  • Country: Spain
  • Page Numbers: pp.280-281
  • Istanbul Kültür University Affiliated: Yes

Abstract

A field programmable gate array (FPGA) implementation of the Gabor-type filter is presented. The implementation uses the forward Euler approximation with optimal step size to solve the CNN cell-state equation. The FPGA is implemented on Xilinx Spartan XC3S400 device using 219 slices. An image of dimension 60 x 60 can be processed without using any external RAM only with the block RAM.